Every FPGA development environment I've used mitigates this issue with an "elaboration" step that parses the code, enumerates the connections, and building a representation of the topological aspect. That's often presented in the graphical form of a block diagram. That way you can see the connections and perceive issues that may not have been obvious in the code.
But again, a block diagram obscures the entire logical functionality of the hardware. It's one perspective or the other.
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